The disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having vertical channels formed in a top-to-bottom direction, which will be referred to as vertical channels hereafter, and method of fabricating the same.
As integration degree of semiconductor devices increases, semiconductor devices having vertical channel formed in a top-to-bottom direction realize a 4F2 structure to improve cell efficiency.
FIG. 1 is a diagram illustrating an exemplary semiconductor device having channels formed in a top-to-bottom direction.
Referring to FIG. 1, the depicted embodiment of a semiconductor device includes a substrate 10, a pillar pattern having a pillar head 11 and a pillar neck 12, a gate hard mask layer 13 for protecting an upper portion of the pillar pattern, a sidewall passivation layer 14 for protecting a sidewall of the pillar head 11, a gate insulation layer 15 surrounding the pillar neck 12, and a gate electrode 16. A source and a drain are formed at the pillar head 11 and the substrate 10, and a channel is formed at the pillar neck 12 through the source and the drain.
However, because the pillar neck 12 of the pillar pattern has a diameter smaller than that of the pillar head 11, and the gate hard mask layer 13 is disposed over the pillar head 11, the pillar pattern sometimes tips to the side or falls down as shown in FIG. 2. Sometimes also due to this structure, adjacent pillar patterns adhere together. Likewise, the pillar pattern sometimes falls down because the pillar neck 12 with a smaller diameter is formed after forming the pillar head 11.
When the pillar head 11 and the pillar neck 12 are etched without an etch stop layer, often the heights of the pillar patterns are not uniform as shown in FIG. 3.
When a gap between the pillar patterns is filled with a conductive layer to form the gate electrode 16, often a void 21 and a seam are formed in the conductive layer due to a high aspect ratio between the pillar patterns as shown in FIG. 4. If the conductive layer is patterned after filling the gap, a punch problem 22 arises due to an etch speed difference caused by the void 21 and the seam. Here, the punch problem 22 attacks the gate insulation layer 15 and the substrate 10 as shown in FIG. 5. Furthermore, the sidewall passivation layer 14 is sometimes damaged due to an etch selectivity in the patterning of the conductive layer as shown in FIG. 6. Consequently, the pillar head 11 is damaged.